Revised February 74AC • 74ACT Synchronous Presettable Binary Counter General Description Features The AC/ACT are high-speed. HE are high-speed synchronous modulo binary counters. A. A brief overview of IC . Synchronous Presettable Binary Counter. The AC/ACT are high- speed synchronous modulo binary counters. They are synchronously presettable.

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Maximum test duration 2. This total delay plus setup time sets the upper limit on clock frequency.

Counter and ROM

Fairchild does not recommend operation of circuits outside databook specifications. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. The circuits have four fundamental modes of operation, in order of precedence: The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters.


All outputs loaded; thresholds on input associated with output under test. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to dstasheet through the intermediate stages.

Life support devices or systems are devices or systems which, a are intended for surgical 7413 into the body, or b support or sustain life, and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

The clock datasbeet of all flip-flops are driven in parallel through a clock buffer. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters.


Datasheet(PDF) – TI store

dattasheet Documents Flashcards Grammar checker. Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Absolute maximum ratings are daasheet values beyond which damage to the device may occur.